ASIC Verification Engineer

About Atos Group

Atos Group is a global leader in digital transformation with c. 67,000 employees and annual revenue of c. €10 billion, operating in 61 countries under two brands — Atos for services and Eviden for products. European number one in cybersecurity, cloud and high performance computing, Atos Group is committed to a secure and decarbonized future and provides tailored AI-powered, end-to-end solutions for all industries. Atos Group is the brand under which Atos SE (Societas Europaea) operates. Atos SE is listed on Euronext Paris.

The purpose of Atos Group is to help design the future of the information space. Its expertise and services support the development of knowledge, education and research in a multicultural approach and contribute to the development of scientific and technological excellence. Across the world, the Group enables its customers and employees, and members of societies at large to live, work and develop sustainably, in a safe and secure information space.

About Eviden

Eviden is the Atos Group brand for hardware and software products with c. € 1 billion in revenue, operating in 36 countries and comprising four business units: advanced computing, cybersecurity products, mission-critical systems and vision AI. As a next-generation technology leader, Eviden offers a unique combination of hardware and software technologies for businesses, public sector and defense organizations and research institutions, helping them to create value out of their data. Bringing together more than 4,500 world-class talents and holding more than 2,100 patents, Eviden provides a strong portfolio of innovative and eco-efficient solutions in AI, computing, security, data and applications.

Title: ASIC Verification Engineer

Location: Bangalore (Whitefield)

Experience: 3-5 years

Education: Bachelor’s degree (BE/B.Tech) or Master’s degree (ME/M.Tech)

Roles & Responsibilities:

• Acquire knowledge microarchitecture an ASIC unit by studying the specification and interacting with the logical design team.
• Write and perform the test plan in close cooperation with the logical design team.
• Develop coverage models and verification environments using UVM-SystemVerilog / C++. Write, maintain and publish the verification specification.
• Monitor, analyze and debug simulation errors.
• Monitor and analyze simulation coverage results to improve tests accordingly thereby achieving coverage targets on time.
• Produce a maintainable and reusable code across projects

Required Skills and Experience

• Curious, demanding and rigorous.
• Mastering object oriented programming.
• Knowledge of UVM verification methodology (or equivalent) and SystemVerilog / SystemC hardware verification languages ​​
• Knowledge of Constraint-Random / Coverage-Driven verification environments development in SystemVerilog / C ++ (drivers / monitors, constraint random tests, checkers and self-checking models and coverage models written in SystemVerilog-Covergrourp / SVA)
• Knowledge of simulation tools and coverage database visualization tools
• Effective in problems solving by rapidly identifying their root cause and developing patches or workarounds under tight timing constraints.

Our Offering:

• Competitive salary package
• Leave Policies: 10 Days of Public Holiday (Includes 2 days optional) & 22 days of Earned Leave (EL) & 11 days for sick or caregiving leave.
• Benefit Plans (Insurance) – Medical & Life & Accidental & EDLI

Let’s grow together.