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Static Timing Analysis Expert Engineer (H/F)

Publish Date:  Sep 24, 2022
Location: 

Les Clayes - 78, Ile-De-France, FR-France

Company:  Atos

About Atos

Atos is a global leader in digital transformation with 110,000 employees in 73 countries and annual revenue of € 12 billion. European number one in Cloud, Cybersecurity and High-Performance Computing, the Group provides end-to-end Orchestrated Hybrid Cloud, Big Data, Business Applications and Digital Workplace solutions. The Group is the Worldwide Information Technology Partner for the Olympic & Paralympic Games and operates under the brands Atos, Atos|Syntel, and Unify. Atos is a SE (Societas Europaea), listed on the CAC40 Paris stock index.


The purpose of Atos is to help design the future of the information space. Its expertise and services support the development of knowledge, education and research in a multicultural approach and contribute to the development of scientific and technological excellence. Across the world, the Group enables its customers and employees, and members of societies at large to live, work and develop sustainably, in a safe and secure information space.

 

 

 

 As part of our ASIC Design & Verification group, you will take part of our next-generation High Performing Computing (HPC) system-on-chip (SoC) design. In this role, you will be responsible for all aspects of timing including, working with designers for timing changes, helping construct/modify flows, timing analysis and timing closure.

 

Key Qualifications:

 

-Working with design teams to understand and debug constraints, facilitate logic changes to improve timing

-Working with Physical Design and Logic Design teams, highlighting issues

-Help create timing ECO’s for project tapeout

We value the ability to create and maintain scripts and methodologies for analysis and runs

-Document and help with guidelines and specs

-Deep analysis of timing paths to identify key issues is critical

-Implement timing infrastructure

Good communicator who can accurately describe issues and follow them through to completion.

Your attention to details will be instrumental to success.

 

Your profil:

 

-Familiar with timing of large high-performance SoC designs in sub-micron technologies.

-Timing Margin Fundamentals from synthesis to signoff.

-Be proficient in STA and standards for timing closure, and have a deep understanding of noise, cross-talk, and OCV effects, among others.

-Familiar with circuit modeling, including SPICE models and worst-case corner selection.

-Strong programming skills with Perl, TCL.

-Timing Flow using industry standard tools

-Experience with STA on large, complex designs and Multi-Scenario Timing Closure.

-Familiarity with ECO techniques and implementation.

 

Education & Experience:

- More than 3 years experience in this role

- MSEE or equivalent is required MSEE or equivalent is required.

 

Location: Ile de France or Sophia Antipolis

 

 

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Here at Atos, we want all of our employees to feel valued, appreciated, and free to be who they are at work. Our employee lifecycle processes are designed to prevent discrimination against our people regardless of gender identity or expression, sexual orientation, religion, ethnicity, age, neurodiversity, disability status, citizenship, or any other aspect which makes them unique. Across the globe, we have created a variety of programs to embed our Atos culture of inclusivity, and work hard to ensure that all of our employees have an equal opportunity to contribute and feel that they are exactly where they belong.